The present invention is directed to power-on-reset circuits and, more particularly, to power-on-reset circuits having low variation in de-assertion threshold voltage.
Power-on-reset (POR) circuits are used in devices such as a system-on-chip (SOC) to keep flip-flops and other sequential elements in a known state (e.g., set or reset) until a proper supply level is reached on start-up. Generally, during power supply ramp-up, the output signal of the POR circuit is kept low. The supply voltage level during ramp-up at which the POR circuit output signal “de-asserts” (i.e., switches to high logic level) is referred to as the de-assertion threshold. FIG. 1 shows an example of a supply voltage level and POR circuit output signal level over time during a ramp-up period.
In a conventional POR circuit, de-assertion occurs while the supply voltage is still climbing, and there can be a wide variation in the de-assertion threshold. Such variation is detrimental to the assurance of a reliable start-up under varying ramp rate conditions.
FIG. 2 is a schematic circuit diagram of a conventional POR circuit 10. The signal por_b on output 12 of the circuit 10 goes high when a supply voltage VDD_POR crosses the de-assertion threshold, which is set by a voltage divider 14 (formed by two resistors 16, 17 and a resistance Rds of a plurality of NMOS transistors 18 connected in series) and a switching threshold of a first inverter 20. The typical de-assertion threshold for a POR circuit implemented in 28 nm CMOS process, for example, is about 700 mV. However, since the POR circuit 10 is an open loop (i.e., no feedback), the threshold can vary significantly across process and temperature variations. For example, the threshold of a POR circuit designed in 28 nm CMOS technology can vary between 500 mV-700 mV.
It is therefore desirable to provide a POR circuit that reduces de-assertion threshold voltage variations while also reducing silicon area.